1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a hierarchical word-line scheme comprising main word-lines and sub-word-lines.
2. Description of the Related Art
Although high integration of a semiconductor memory device, especially, a DRAM has rapidly advanced in recent years, a reduction in word-line rising speed due to an increase in load capacitance at word-line rising involved due to an increase in memory capacity and an increase in current consumption have become a problem.
In general, a word-line rising time is dependent on a wiring resistance of word-lines, a wiring resistance of a load capacitance and a word-line driving current supply circuit, and a load capacitance. For example, in Jpn. Pat. Appln. KOKAI Publication No. 7-130168, a split decode scheme by which a word-line is divided into a plurality of lines and a current supply word-line driver is provided for each of the divided word-lines is adopted in order to increase the word-line driving speed, and a word-line driving current is supplied to word-line drivers in the same column through at least two signal lines. With such a configuration, since the number of word-line drivers per word-line driving current supply signal is reduced, i.e., since a load capacitance of the word-line driving current supply circuit is reduced, a rising speed of the word-lines is increased, thereby reducing current consumption when driving the word-lines.
Further, as means for reducing a resistance by substantially shortening a word-line length, there is known a DRAM adopting a hierarchical word-line scheme in which one main word-line is divided into a plurality of sub-word-lines and a sub-word-line driver is provided for each of the divided sub-word-lines. More specifically, this is a scheme in which a memory cell array is divided into a plurality of sub-arrays in a word-line direction, a plurality of main word-lines branch out in accordance with each sub-array, and a sub-word-line driver which receives an address signal through the main word-line which is provided for and corresponds to each sub-array selectively drives a plurality of associated sub-word-lines. A driver which drives the sub-word-lines upon receiving addresses from the main word-lines is disclosed in, e.g., U.S. Pat. No. 6,229,755B1, and is a driver which supplies boosted address signals to the sub-word-lines based on address signals of the main word-lines activated by a boosted potential VPP.
In the above-described hierarchical word-line scheme, since the main word-lines branch out to the plurality of sub-word-lines and a desired sub-word-line is selectively driven, the resistance of the word-lines can be reduced, and the word-line selection operation speed can be thereby increased. In such a hierarchical word-line scheme, however, a boosted potential VPP must be supplied to a related driver in order to activate an arbitrary word-line. Consequently, in the case of a semiconductor memory device comprising a boosted potential (VPP) generator or a decoupling capacitor which stabilizes a boosted potential as an internal circuit, a layout area of a charge-pump circuit or the decoupling capacitor constituting the boosted potential generator is increased, leading to an increase in a chip area.
In the semiconductor memory device adopting the hierarchical word-line scheme, therefore, there has been demanded a realization of a semiconductor memory device which can reduce power losses in main word-lines, and reduce the entire chip area by decreasing the area required for an internal boosted potential generator or decoupling capacitor.